module clk_divider_7 (
    input  clk_in,
    input  reset_n,
    output clk_out
);

    reg [2:0] count_rise;
    reg [2:0] count_fall;
    
    // 分别用两个信号来处理上升沿和下降沿的输出
    reg clk_rise_out;
    reg clk_fall_out;
    
    // 组合两个信号生成最终的7分频时钟
    assign clk_out = clk_rise_out | clk_fall_out;

    // --- 上升沿处理
    always @(posedge clk_in or negedge reset_n) 
    begin
        if (!reset_n) begin
            count_rise <= 3'd0;
            clk_rise_out <= 1'b0;
        end
        else begin
            if (count_rise == 3'd6) begin
                count_rise <= 3'd0;
            end
            else begin
                count_rise <= count_rise + 1;
            end
            
            // 在计数0-3期间输出高电平
            if (count_rise >= 3'd0 && count_rise <= 3'd2) begin
                clk_rise_out <= 1'b1;
            end
            else begin
                clk_rise_out <= 1'b0;
            end
        end
    end

    // --- 下降沿处理
    always @(negedge clk_in or negedge reset_n) begin
        if (!reset_n) begin
            count_fall <= 3'd0;
            clk_fall_out <= 1'b0;
        end
        else begin
            if (count_fall == 3'd6) begin
                count_fall <= 3'd0;
            end
            else begin
                count_fall <= count_fall + 1;
            end

            // 在特定计数期间输出高电平，与上升沿配合形成占空比接近50%的7分频
            if (count_fall >= 3'd0 && count_fall <= 3'd2) begin
                clk_fall_out <= 1'b1;
            end
            else begin
                clk_fall_out <= 1'b0;
            end
        end
    end

endmodule